D Latch

Introduction

A D latch is a level-sensitive memory element that stores one bit of data. When the enable (EN) signal is high, the output follows the D input. When EN is low, the output holds the previously stored value.

Problem Statement

Design a D latch that stores the input value when enable is high and holds the value when enable is low.

Specifications

Inputs: D (Data), EN (Enable)

Output: Q (Stored bit)

Operation: Q = D when EN=1, otherwise Q holds its value

Truth Table

Verilog RTL Code

Verilog

module d_latch (
input wire D,
input wire EN,
output reg Q
);
always @ (D or EN) begin
if (EN)
Q <= D;
end
endmodule

Testbench Code

Verilog

module tb_d_latch();
reg D, EN;
wire Q;

d_latch tb_d_latch (.D(D), .EN(EN), .Q(Q));

initial begin
$monitor("Time=%0t | EN=%b D=%b | Q=%b", $time, EN, D, Q);
EN = 0; D = 0;
#5 D = 1;
#5 EN = 1;
#5 D = 0;
#5 EN = 0; D = 1;
#5 EN = 1;
#5 $finish;
end
endmodule

Interview Questions & Answers

Q1. Why are latches called 'transparent' devices?

Answer:
A latch is called transparent because, when it’s enable signal is active, any change at the input instantly appears at the output. It’s like looking through a glass window — you see exactly what’s on the other side. When enabled, even tiny glitches in the input will pass through, which is why designers must be careful. When disabled, it becomes 'opaque' and holds its last value.

Q2. What is the main disadvantage of using latches in synchronous systems?

Answer:
Latches are level-sensitive, meaning they respond to the input as long as the enable signal is active. This can allow unwanted changes or “glitches” to pass through if the input changes at the wrong time. In synchronous systems, where precise timing is critical, this can make timing analysis harder and may lead to unpredictable results. That’s why designers often prefer edge-triggered flip-flops, which only react at a single moment in time.

Q3. How can you convert an SR latch to a D latch?

Answer:
To turn an SR latch into a D latch, you connect:

S input connected directly to D
R input connected to the opposite of D (NOT D)

This way:

If D = 1 , S = 1, R = 0 then latch sets Q
If D = 0 , S = 0, R = 1 then latch resets Q
It guarantees that S and R are never 1 at the same time, removing the “invalid” state.

Q4. Why is there an 'invalid' state in SR latches and how can it be avoided?

Answer:
In a NOR-based SR latch, when S = 1 and R = 1 at the same time, both outputs try to become 0. This breaks the rule that Q and Q̅ should be exact opposites that’s the “invalid” state. To avoid it:

Ensure the inputs never go high together (add control logic)
Or use a D latch or JK latch, which is designed to avoid this problem entirely

Q5. Why might latches cause race conditions in digital designs?

Answer:
Because latches are level-sensitive, the output can change multiple times while the enable signal is active. If one latch’s output is connected to another latch that is also enabled at the same time, signals can keep bouncing back and forth in the same clock period — that’s called a race condition. This can cause unstable or unpredictable results.

Q6. If a D latch has a propagation delay of 4 ns and EN is high for 10 ns, how many times can Q change?

Answer:

In theory, Q could change at most twice. This is because after each change, it takes 4 ns before the output can respond to a new change at the input. With EN high for 10 ns, only two changes can fit within that time.

Q7. What happens if EN is tied permanently high in a noisy signal environment?

Answer:
If EN is always high, the latch behaves like a simple wire — any change at D immediately appears at Q. In a noisy environment, even tiny spikes or unwanted changes at D will go straight to Q, possibly causing wrong outputs. This defeats the purpose of having a latch.

Q8. In an SR latch, if S goes high and R also goes high after 1 ns, what happens to Q?

Answer:

It depends on the delays inside the latch:

First, S = 1 will try to set Q to 1

Then, R = 1 arrives and tries to reset Q to 0
The short gap may cause Q to briefly be 1, then 0. In some cases, the latch might enter metastability, where it’s stuck in an unstable state for a short time before settling.

Q9. Can a latch be used to remove glitches?

Answer:

Yes, but only if the enable signal is low during the glitch. When EN is low, the latch holds its last value and ignores input changes. This is sometimes used to “filter” out short unwanted pulses.

Q10. What is the difference in setup and hold times for a latch compared to a flip-flop?

Answer:

For a latch, setup and hold times are measured relative to when the enable signal is active, not a clock edge. This means you must keep the input stable just before and after EN goes high. For a flip-flop, these times are measured around the moment of the clock edge (rising or falling).

Q11. Why might synthesizing the following code result in a latch?

always @(*) if (EN) Q = D;

Answer:

Because there’s no “else” part. When EN is 0, the code does not say what Q should be, so the tool assumes Q must remember its old value and that means a latch is needed.

Q12. How can you avoid latch inference in combinational logic in Verilog?

Answer:

Make sure you assign a value to every output in all possible cases. For example:

always @(*) begin

Q = 0; // default

if (EN) Q = D;

end

This way, Q is always defined, and there’s no need to store an old value.

Q13. What happens if Q is not initialized in a latch simulation?

Answer:

It will start as “X” (unknown) in simulation. This unknown value stays until EN goes high for the first time and Q gets a real value.

Q14. Why is it dangerous to infer latches unintentionally in FPGA/ASIC designs?

Answer:

Unplanned latches can cause unpredictable timing, make it harder for tools to optimize the circuit, and increase power usage. They also make testing more complicated because their behavior can depend on when EN is active, not just on the clock.

Q15. Write Verilog code for a latch that toggles output when EN=1 and D changes, but ignores very fast changes.

Answer:

You can use a debounce filter a small circuit or delay that only accepts changes if they stay for a certain time. Example:

module debounce_latch(input D, EN, clk, output reg Q);

reg D_stable;

always @(posedge clk) begin

if (EN) begin

if (D == D_stable) Q <= ~Q;

D_stable <= D;

end

endmodule

Here, D is sampled and compared to its previous stable value to ignore quick, unwanted changes.

Introduction

D Latch

Introduction

Problem Statement

Specifications

Truth Table

Verilog RTL Code

Testbench Code

Interview Questions & Answers

Q3. How can you convert an SR latch to a D latch? Answer: To turn an SR latch into a D latch, you connect:

S input connected directly to D

R input connected to the opposite of D (NOT D)

This way:

If D = 1 , S = 1, R = 0 then latch sets Q

If D = 0 , S = 0, R = 1 then latch resets Q It guarantees that S and R are never 1 at the same time, removing the “invalid” state.

​

​

Q4. Why is there an 'invalid' state in SR latches and how can it be avoided?

Answer: In a NOR-based SR latch, when S = 1 and R = 1 at the same time, both outputs try to become 0. This breaks the rule that Q and Q̅ should be exact opposites that’s the “invalid” state. To avoid it:

Ensure the inputs never go high together (add control logic)

Or use a D latch or JK latch, which is designed to avoid this problem entirely

​

​

Q5. Why might latches cause race conditions in digital designs?

​

​

​

Q6. If a D latch has a propagation delay of 4 ns and EN is high for 10 ns, how many times can Q change?

​

Answer:

In theory, Q could change at most twice. This is because after each change, it takes 4 ns before the output can respond to a new change at the input. With EN high for 10 ns, only two changes can fit within that time.

​

​

Q7. What happens if EN is tied permanently high in a noisy signal environment?

​

Answer: If EN is always high, the latch behaves like a simple wire — any change at D immediately appears at Q. In a noisy environment, even tiny spikes or unwanted changes at D will go straight to Q, possibly causing wrong outputs. This defeats the purpose of having a latch.

​

​

Q8. In an SR latch, if S goes high and R also goes high after 1 ns, what happens to Q?

Answer:

It depends on the delays inside the latch:

First, S = 1 will try to set Q to 1

​

Then, R = 1 arrives and tries to reset Q to 0 The short gap may cause Q to briefly be 1, then 0. In some cases, the latch might enter metastability, where it’s stuck in an unstable state for a short time before settling.

​

​

Q9. Can a latch be used to remove glitches?

​

Answer:

Yes, but only if the enable signal is low during the glitch. When EN is low, the latch holds its last value and ignores input changes. This is sometimes used to “filter” out short unwanted pulses.

​

​

Q10. What is the difference in setup and hold times for a latch compared to a flip-flop?

Answer:

For a latch, setup and hold times are measured relative to when the enable signal is active, not a clock edge. This means you must keep the input stable just before and after EN goes high. For a flip-flop, these times are measured around the moment of the clock edge (rising or falling).

​

​

Q11. Why might synthesizing the following code result in a latch?

always @(*) if (EN) Q = D;

​

Answer:

Because there’s no “else” part. When EN is 0, the code does not say what Q should be, so the tool assumes Q must remember its old value and that means a latch is needed.

​

​

Q12. How can you avoid latch inference in combinational logic in Verilog?

​

Answer:

Make sure you assign a value to every output in all possible cases. For example:

always @(*) begin

Q = 0; // default

if (EN) Q = D;

end

This way, Q is always defined, and there’s no need to store an old value.

​

​

Q13. What happens if Q is not initialized in a latch simulation?

​

Answer:

It will start as “X” (unknown) in simulation. This unknown value stays until EN goes high for the first time and Q gets a real value.

​

​

Q3. How can you convert an SR latch to a D latch?

Answer:
To turn an SR latch into a D latch, you connect:

If D = 0 , S = 0, R = 1 then latch resets Q
It guarantees that S and R are never 1 at the same time, removing the “invalid” state.

Answer:
In a NOR-based SR latch, when S = 1 and R = 1 at the same time, both outputs try to become 0. This breaks the rule that Q and Q̅ should be exact opposites that’s the “invalid” state. To avoid it:

Answer:
If EN is always high, the latch behaves like a simple wire — any change at D immediately appears at Q. In a noisy environment, even tiny spikes or unwanted changes at D will go straight to Q, possibly causing wrong outputs. This defeats the purpose of having a latch.

Then, R = 1 arrives and tries to reset Q to 0
The short gap may cause Q to briefly be 1, then 0. In some cases, the latch might enter metastability, where it’s stuck in an unstable state for a short time before settling.