T Latch
Introduction
A T latch (Toggle latch) changes its output state when the T input is high and enable is active. If T is low, the output remains the same.
Problem Statement
Design a T latch that toggles the output when T is high and holds the output when T is low.
Specifications
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Inputs: T (Toggle), EN (Enable)
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Output: Q
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Operation: Q toggles when T=1 and EN=1
Truth Table
Verilog RTL Code
Verilog
module t_latch (
input wire T,
input wire EN,
output reg Q
);
always @ (T or EN) begin
if (EN) begin
if (T)
Q <= ~Q;
end
end
endmodule
Testbench Code
Verilog
module tb_t_latch();
reg T, EN;
wire Q;
t_latch tb_t_latch (.T(T), .EN(EN), .Q(Q));
initial begin
$monitor("Time=%0t | EN=%b T=%b | Q=%b", $time, EN, T, Q);
EN = 0; T = 0;
#5 EN = 1; T = 1;
#5 T = 0;
#5 T = 1;
#5 EN = 0; T = 1;
#5 $finish;
end
endmodule
Interview Questions & Answers
Q1. Why is the T latch called a “toggle” latch?
Answer:
Because when T=1 and the latch is enabled, the output switches (toggles) from 0 to 1 or 1 to 0 every time it’s enabled again. If T=0, it simply holds its previous value.
Q2. How is a T latch constructed from a JK latch?
Answer:
Tie J and K together and feed them with the T input. This makes the JK latch toggle whenever T=1 and hold when T=0.
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Q3. What happens if T=1 and enable is high for a long period in a level-sensitive T latch?
Answer:
The output will keep toggling repeatedly during the enable period, causing race-around condition if propagation delay allows multiple toggles.
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Q4. How can the race-around problem be avoided in a T latch?
Answer:
Make it edge-triggered (T flip-flop) so toggling occurs only on a specific clock edge, or ensure enable pulses are shorter than the propagation delay.
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Q5. If a T latch is initialized to Q=0, and T=1 with enable high for 30 ns, and the propagation delay is 5 ns, how many toggles occur?
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Answer:
At most 6 toggles (30 ÷ 5 = 6). In practice, feedback delay may slightly reduce the number.
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Q6. Why is a T latch useful for frequency division?
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Answer:
When edge-triggered, it toggles exactly once per enable/clock pulse, producing an output frequency exactly half the input frequency — perfect for clock division.
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Q7. How can a T latch be implemented using an SR latch?
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Answer:
Add XOR logic before the SR latch: feed Q XOR T to the S input and ~Q XOR T to the R input. This makes Q toggle when T=1 and hold when T=0.
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Q8. Why is a T latch not often used in isolation in synchronous designs?
Answer:
Because controlling the enable period is tricky, and race-around can cause unpredictable results. Instead, designers use T flip-flops with edge-triggering.
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Q9. What happens if T=0 in a T latch for a very long time?
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Answer:
The output remains unchanged indefinitely, acting like a memory cell holding the last state.
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Q10. How does power consumption in a T latch compare to a D latch?
Answer:
If T is low most of the time, the T latch consumes less dynamic power because it doesn’t change state often. If T is high constantly, it can consume more due to continuous toggling.
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Q11. If you connect T=1 permanently in a T latch, what does it become?
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Answer:
It becomes a free-running toggle that changes state every time it’s enabled — essentially a frequency divider by 2.
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Q12. How does metastability occur in a T latch?
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Answer:
If T or enable changes very close to a propagation delay boundary, the latch may not settle to a clean 0 or 1 immediately, causing uncertain output for a short time.
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Q13. Why is the T latch sometimes referred to as a “1-bit counter”?
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Answer:
Because toggling effectively counts:
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Q=0 → first toggle → Q=1
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Q=1 → second toggle → Q=0
This sequence is equivalent to counting modulo 2.