JK Flip-Flop in Verilog – Design & Simulation

Flip-flops are essential building blocks in digital electronics, used to store and control binary data. Among them, the JK flip-flop is called a universal flip-flop because it can function as an SR, D, or T flip-flop depending on how its inputs are configured.

In this post, we’ll explore what a JK flip-flop is, how it works, and how to implement it in Verilog HDL with asynchronous preset and clear functionality.

1. What is an SR Flip-Flop?

A JK flip-flop is a clocked storage element with two inputs:

J (Set input)
K (Reset input)

It extends the functionality of the SR flip-flop by resolving the invalid state (S=1, R=1).

When both J and K are high, the JK flip-flop toggles its output.

2. Problem Statement

Goal:

Design a positive-edge triggered JK flip-flop in Verilog that supports:

Asynchronous reset (active-high) – clears output immediately.
Asynchronous preset (active-high) – sets output immediately.

3. Truth Table

J K Q(next) Description

0 0 Q(prev) Hold

0 1 0 Reset

1 0 1 Set

1 1 ~Q(prev) Invalid

3. Verilog Code

Verilog

module jk_ff (
input wire J,
input wire K,
input wire clk,
input wire arst, // async reset
input wire aset, // async preset
output reg Q
);
always @(posedge clk or posedge arst or posedge aset) begin
if (arst) Q <= 1'b0;
else if (aset) Q <= 1'b1;
else begin
case ({J,K})
2'b00: Q <= Q;
2'b01: Q <= 1'b0;
2'b10: Q <= 1'b1;
2'b11: Q <= ~Q;
endcase
end
end
endmodule

Explanation:

posedge clk ensures synchronous updates.
posedge arst / posedge aset handle asynchronous control signals.
case statement provides a clean mapping from input combinations to output actions.

Verilog

module tb_jk_ff;
reg J, K, clk, arst, aset;
wire Q;

jk_ff tb_jk_ff_VM (.J(J), .K(K), .clk(clk), .arst(arst), .aset(aset), .Q(Q));

initial clk = 0;
always #5 clk = ~clk;

initial begin
arst = 0; aset = 0; J = 0; K = 0; #10;
J = 1; K = 0; #10;
J = 0; K = 1; #10;
J = 1; K = 1; #20;
$finish;
end

initial begin
$dumpfile("tb_jk_ff.vcd"); // Waveform dump file
$dumpvars(1, tb_jk_ff); // Dump all signals in testbench and DUT
end

initial begin
$monitor("Time=%0t | J=%b K=%b arst=%b aset=%b clk=%b Q=%b",
$time, J, K, arst, aset, clk, Q);
end
endmodule

Key points in testbench:

The clock toggles every 5 time units.
Both set, reset, and toggle behaviors are verified.
Asynchronous controls can be added in the test to check immediate response.

6. Simulation Waveform (Expected)

J=1, K=0: Output goes to 1 at the next clock edge.
J=0, K=1: Output goes to 0 at the next clock edge.
J=0, K=0: Output holds its previous value.
J=1, K=1: Output toggles on each clock edge.

7. Conclusion

The JK flip-flop is one of the most flexible sequential elements in digital logic.

With just two inputs, it can mimic:

SR flip-flop (Set/Reset behavior)
D flip-flop (by tying K to ~J)
T flip-flop (by tying J and K together)

Adding an asynchronous preset and clear makes it suitable for applications requiring immediate initialization or forceful state changes.