D (Data) Flip-Flop in Verilog – Design & Simulation
In digital electronics, flip-flops are memory elements that store binary values. Among them, the D (Data) flip-flop is one of the simplest and most widely used types. In this post, we’ll understand what a D flip-flop is, how it works, and how to implement it in Verilog HDL along with a testbench.
1. What is an SR Flip-Flop?
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A D flip-flop captures the value at the D (Data) input on the active clock edge and holds it until the next capture.
It has:
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One data input (D)
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One output (Q)
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A clock input (clk)
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Optional reset (for initialization)
Unlike the SR flip-flop, the D flip-flop eliminates the invalid state (S=1, R=1) by design.
2. Problem Statement
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Goal:
Design an positive edge-triggered D flip-flop in Verilog with an asynchronous active-high reset.
3. Truth Table​
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D CLK Q(next) Description
0 0->1 0 Hold
1 0->1 1 Reset
X no edge Q(prev) Set
3. Verilog Code​
Verilog
module d_ff (
input wire D,
input wire clk,
input wire arst, // active-high async reset
output reg Q
);
always @(posedge clk or posedge arst) begin
if (arst) Q <= 1'b0;
else Q <= D;
end
endmodule
Explanation:
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posedge clk → Captures the value of D only at the rising edge.
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posedge arst → Resets output Q to 0 immediately (asynchronous behavior).
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This design ensures predictable operation without invalid states.
Verilog
module tb_d_ff;
reg D, clk, arst;
wire Q;
d_ff tb_d_ff_VM (.D(D), .clk(clk), .arst(arst), .Q(Q));
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initial clk = 0;
always #5 clk = ~clk;
initial begin
arst = 1; D = 0; #8;
arst = 0; #10;
D = 1; #10;
D = 0; #10;
$finish;
end
// Waveform dumping
initial begin
$dumpfile("tb_d_ff.vcd");
$dumpvars(1, tb_d_ff.uut); // dump all signals in DUT instance recursively
end
// Display signals when changed
initial begin
$monitor("Time=%0t | D=%b arst=%b clk=%b Q=%b", $time, D, arst, clk, Q);
end
endmodule
Key points in testbench:
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Clock signal toggles every 5 time units.
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Reset is applied at the start to initialize Q.
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Data changes are applied before clock edges to see correct capture behavior.
6. Simulation Waveform (Expected)
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At reset, Q is forced to 0 immediately.
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On each rising clock edge, Q updates to match D.
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Between clock edges, Q holds its previous value.
7. Conclusion
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The D flip-flop is a fundamental sequential element in digital design.
It’s widely used in:
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Registers
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Counters
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Data storage elements
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Pipeline stages in processors
By adding an asynchronous reset, we ensure the circuit can be initialized to a known state at any time.
8. CLICK ON BELOW LOGO to run the Verilog Code on EDA PLAYGROUND.
