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T (Toggle) Flip-Flop in Verilog – Design & Simulation

The T (Toggle) flip-flop is a simple yet powerful sequential circuit widely used in counters and frequency division applications. It changes (toggles) its output state only when the T input is high during the active clock edge; otherwise, it holds its current state.

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In this article, we’ll explain the T flip-flop’s working, design a positive-edge triggered T flip-flop in Verilog, and verify it with a simulation testbench.

1. What is an T Flip-Flop?

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A T flip-flop :

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  • Toggles its output when T = 1 at the clock edge.
     

  • Holds its output when T = 0.
     

  • Is often used for frequency division (output frequency = input clock frequency ÷ 2 for continuous toggle).

2. Problem Statement

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Goal:

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Design a positive-edge triggered T flip-flop in Verilog with synchronous enable control.

3. Truth Table​

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    T        CLK             Q(next)        Description

    0        0->1            Q(prev)         Hold

    1        0->1            ~Q(prev)       Reset

3. Verilog Code​

 Verilog

module d_ff (
    input wire T,
    input wire clk,
    input wire en,
    output reg Q
);

  always @(posedge clk) begin
    if
(en) begin

      if (T) Q <= ~Q;
      else Q <= Q;
    end

    else

      Q <= 0;

  end
endmodule

Explanation:

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  • posedge clk ensures the flip-flop updates only at the rising clock edge.
     

  • Enable signal (en) controls whether toggling/holding occurs.
     

  • When en = 0, output remains unchanged regardless of T.

 Verilog

module tb_t_ff;

  reg T, clk, en;

  wire Q;

 

  t_ff tb_t_ff_VM(.T(T), .clk(clk), .en(en), .Q(Q));

 

  initial clk = 0;

  always #5 clk = ~clk;

​

  initial begin

    en = 0; T = 0; #10;

    en = 1; T = 1; #20;  // toggling

    T = 0; #10;

    $finish;

  end

 

  // Waveform dump

  initial begin

    $dumpfile("tb_t_ff.vcd");

    $dumpvars(1, tb_t_ff);

  end

 

  // Monitor signals changes

  initial begin

    $monitor("Time=%0t | T=%b en=%b clk=%b Q=%b", $time, T, en, clk, Q);

  end

endmodule

Key points in testbench:

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  • The clock toggles every 5 time units.
     

  • Different T values are applied to check hold and toggle behaviors.
     

  • Enable is kept active (en = 1) throughout for simplicity.

6. Simulation Waveform (Expected)

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  • T = 1: Output toggles on each rising clock edge (e.g., 0 → 1 → 0 → 1).
     

  • T = 0: Output holds its previous value.
     

  • With en = 0 (not shown in example): Output would freeze regardless of T.

7. Conclusion

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The T flip-flop is a key element in:

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  • Counters (ripple and synchronous)
     

  • Frequency dividers
     

  • Toggle-based control systems
     

Adding a synchronous enable makes it more versatile in controlled toggling applications.

8. CLICK ON BELOW LOGO to run the Verilog Code on EDA PLAYGROUND.

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