Verilog HDL

HDLs provide ways to represent the digital circuits in the textual form. Verilog HDL is a HARDWARE DESCRIPTION LANGUAGE to model the digital circuits, the source code is written in a text file with the extension [*. v].

Any Verilog HDL source code is created with the combination of IDENTIFIERS and KEYWORDS which are also called as SYNTAX/SEMANTICS. These are globally called lexical tokens. Combination of more than one lexical token originate LEXICAL CONVENTIONS.

Introduction & Overview of Verilog HDL
Typical VLSI Design Flow
RTL Designing
Lexical Conventions
Variables & Data Types and Vector Arrays
Design and Testbench Creation
Verilog Operators and Operands
Gate-Level Modeling/Designing of Digital Circuits
Switch-Level Modeling/Designing
Data-Flow Modeling/Designing
Behavioural Modeling/Designing
Tasks & Functions
User Defined Primitives (UDPs)
Timing Regions
Specify Block
Timing Checks
System Task & Functions
Compiler Directives