System Verilog
As we know, HDLs provide ways to represent the digital circuits in the textual form. Verilog HDL is a HARDWARE DESCRIPTION LANGUAGE to model the digital circuits, the source code is written in a text file with the extension [*. v]. [Click here for Verilog]
​
System Verilog is of both types HARDWARE DESCRIPTION LANGUAGE (HDL) and HARDWARE VERIFICATION LANGUAGE (HVL). It is also called as enhancement of Verilog HDL. The source code is written in a text file with the extension [*. sv].
Any System Verilog source code is created with the combination of IDENTIFIERS and KEYWORDS which are also called as SYNTAX/SEMANTICS. All the lexical conventions of Verilog HDL are supported in System Verilog.
​
We can say that (Verilog + OOPs = System Verilog). But, its not the complete difference among both the languages. ​
All the concepts in Verilog are enhanced in System Verilog, we have explained each and every concepts of System Verilog in relation with Verilog so that readers can easily imagine the connection between Verilog and System Verilog.
​
Below points describes the few more differences between Verilog and SV:
Verification Enhancements
-
Objected Oriented Programming (OOPs): concepts are newly added in System Verilog for creating highly scalable and reusable testbench to verify high performance designs.
-
Interface: is newly added for resolving connection related issues between complex designs and testbench.
-
Randomization: is the key concept for generating random inputs. Constraints are also added for limitation of range in which generated input value lies.
-
Coverage: is introduced for capturing the information of the design and testbench while running the simulations.
-
Assertions: are added for verification of particular part of design directly without running simulations.
-
Packages, Program Block, Inter Process Communication (IPC)- Mailbox and Semaphore: are newly added for making smooth verification process.
Designing Enhancements
-
Port Mapping Rules: are added for better connections between design hierarchy.
-
Behavioural Blocks: Three procedural blocks are newly added for resolving ambiguity errors as well as design blockage/deadlock issue.
-
always_comb: models combinational circuits.​
-
always_latch: models latch circuits.
-
always_ff: models flip flop circuits.
-
-
Task & Function: are enhanced for introducing better reusability and splitting the larger code into smaller parts.​
-
Operator and Loop: are enhanced for reducing the complexity of boolean expression.
-
Lexical Conventions: are enhanced for better control over the language.
-
Introduction to System Verilog
-
​Literal Values
-
Data Types
-
Arrays
-
Operators and Expressions
-
Loops and Multi-way Branching Statements
-
Procedural Blocks and Processes
-
Task and Function
-
Interface, Virtual Interface, and Modport
-
Clocking Blocks
-
Program Block, Packages and Final Block
-
Casting and Events
-
Semaphore and Mailbox
-
Object Oriented Programming (OOPs)
-
Randomization and Constraints
-
Coverage
-
Assertions
-
Testbench Environment Creation
-
Direct Programming Interface (DPI)
-
UVM Pre-requisite