1. Lexical Conventions

Any Verilog HDL source code is created with the combination of IDENTIFIERS and KEYWORDS which are also called as SYNTAX/SEMANTICS. These are globally called lexical tokens. Combination of more than one lexical token originate LEXICAL CONVENTIONS.
Lexical conventions are set of important methods and techniques to write and understand the Verilog HDL code with ease.
Lexical tokens in Verilog HDL are given below:

1.1 white space or blank spaces requirements

White spaces are used in the strings which can be incorporated using the double quotes (“). Follow the below table containing the semantics required to provide the white spaces in the string sequence:

ESCAPE STRING

Character produced by escape string

\n

New line character

Example - 1:
module wh_sp;
initial begin
$display("This is First Line.\nThis is second line.");
end
endmodule

Output:
This is First Line.
This is second line.

\t

TAB character

Example - 2:
module tb_char;
initial begin
$display("This is First Line.\tThis is second line.");
end
endmodule

Output:
This is First Line. This is second line.

\\

\ character

Example - 3:
module backslash_char;
initial begin
$display("This is First Line.\\ This is second line.");
end
endmodule

Output:
This is First Line.\ This is second line.

\"

" character

Example - 4:
module str_char;
initial begin
$display("This is First Line. \"This is second line.\"");
end
endmodule

Output:
This is First Line. "This is second line."

\ddd

A character specified in 1-3 octal digits (0 <=d <= 7).

If less than three characters are used, the following character shall not be an octal digit.
Implementations may issue an error if the character represented is greater than \377.

Example - 4:
module octal_example;
reg [7:0] data;
initial begin
// Assign an octal value to the 'data' register
data = "\123"; // Octal 123 is equivalent to decimal 83
// Display the value in different formats
$display("Octal value: %o", data); //Display in octal
$display("Decimal value: %d", data); //Display in decimal
$display("Hexadecimal value: %h", data);//Display in hexadecimal
end
endmodule

Output:
Octal value: 123
Decimal value: 83
Hexadecimal value: 53

1.2 Comments Implementation

Comments are used to increase the readability of code.

Comments are specifically added in the code for future reference by the designers.

Comments are ignored by the Simulator.

Verilog HDL has two types of comment which are given below:

1.2.1 Single Line Comment

// This line is commented.

Output:

This is ”System Design Verification”.

1.2.2 Multi-line Comment

/* This line is commented.

This line is commented too. */

//Example - 1:

module slc;

initial begin

//$display (“Here, you can learn System Verilog and UVM.”);

$display (“This is \”System Design Verification\”.);

end

endmodule

Output

Verilog

This is "System Design Verification".

Verilog

module mlc;

initial begin

/*

$display (“Here, you can learn System Verilog and UVM.”);

$display (“Here, you can learn Verilog and Digital Electronics.”);

$display (“Here, you can learn LINUX and UNIX.”);

$display (“Here, you can learn PERL and PYTHON.”);

*/

$display (“This is \”System Design Verification\”.);

end

endmodule

Output

This is "System Design Verification".

1.3 OPERATOR USAGE

Operators perform operations on operands.

Operator: The operation which is to be performed.

Operand: The operation on which to be performed.

e.g.,

a + b

The variables `a` and `b` are operands.

The symbol `+` is operator.

There are three kinds of operators available in Verilog HDL which are given below:

1.3.1. Unary Operator: work on single operand.

1.3.2. Binary Operator: work on two operands.

1.3.3. Ternary Operator: work on three operands.

Verilog

module u_op;

reg a;

initial begin

if (!a) begin // ! is a unary operator

$display (“This is Unary Operator example”);

end

initial begin

a = 0;

end

endmodule

Output

This is Unary Operator example.

Verilog

module b_op;

reg a, b = 0, c = 1;

initial begin

$display (“a = %b”, a);

end

initial begin

a = b & c; // & is binary operator

end

endmodule

Output

a = 0

Verilog

module wh_sp;

reg a, b, s; wire y;

assign y = (s == 0) ? a : b; // ()?: is ternary operator

initial begin

$monitor (“a = %b, b = %b, s = %b, y = %b”, a, b, s, y);

a = 1; b = 0; s = 0;

a = 0; b = 0; s = 0;

a = 0; b = 1; s = 1;

a = 0; b = 0; s = 1;

end

endmodule

Output

a = 1, b = 0, s = 0, y = 1

a = 1, b = 0, s = 0, y = 0

a = 1, b = 0, s = 0, y = 1

a = 1, b = 0, s = 0, y = 0

1.4 Numbers Representation

Constant numbers are represented in two ways:

Integer Constants
Real Constants

1.4.1 Integer Constants

Integer constants can be specified in decimal, hexadecimal, octal, or binary format.

There are two forms to express integer constants which are given below:

A. Unsized Number: Simple decimal number, a sequence of digits [0-9], optionally starting with a plus or minus unary operator.

e.g., 19091, +19382, -91289.

B. Sized Number: Based constant, which shall be composed of up to three tokens.

an optional size constant, shall specify the size of the constant in terms of its exact number of bits.
an apostrophe character (', ASCII 0x27) followed by a base format character, shall consist of a case insensitive letter specifying the base for the number. Legal base specifications are d, D, h, H, o, O, b, or B, for the base’s decimal, hexadecimal, octal, and binary respectively. The apostrophe character and the base format character shall not be separated by any white space.
the digits representing the value of the number.

It shall be legal to macro substitute these three tokens.

Negative Constant Numbers

Simple decimal numbers without the size and the base format shall be treated as signed integers,

whereas the numbers specified with the base format shall be treated as signed integers if the s designator is included or as unsigned integers if the base format only is used.

The s designator does not affect the bit pattern specified, only its interpretation.

A plus or minus operator preceding the size constant is a unary plus or minus operator.

e.g., -4 or +4

A plus or minus operator between the base format and the number is an illegal syntax.

Unsized Constant Numbers

Numbers specified without a base format are considered as decimal numbers by default. Numbers that are written without size are simulator/machine specific but must be at least 32 bits.

Sized Constant Numbers

X or Z Values

The default length of x and z is the same as the default length of an integer.

1.4.2 Real Constants

Real numbers are specified as given below:

decimal notation (e.g., 14.72)
scientific notation (e.g., 39e8)
scaled notation (e.g., 24.7K)

Real numbers expressed with a decimal point shall have at least one digit on each side of the decimal point.

Underscore Character

The underscore character is legal anywhere in an integer constant.

The underscore character is legal anywhere in a real constant except as the first character of the constant or the first character after the decimal point. The underscore character is ignored by the simulator.

Verilog

-4'd7 // Used for performing unsigned integer math, will be stored as 2's complement of 7

-4'sd7 // Used for performing signed integer math

4'd-7 // Illegal

Verilog

659 // is a decimal number

'h 837FF // is a hexadecimal number

'o7460 // is an octal number

4af // is illegal (hexadecimal format requires 'h)

Verilog

4'b1001 // is a 4-bit binary number

'D 3 // is a 5-bit decimal number (Simulator/Machine Specific)

Verilog

3'b01x // is a 3-bit number with the least significant bit unknown

12'hx // is a 12-bit unknown number

16'hz // is a 16-bit high-impedance number

16'sd? // the same as 16'sbz

Verilog

E.g., 16’b1011_1000_1111_1010 // Underscore increase the readability of a number constant

1.5 String

A string is a sequence of characters enclosed by double quotes (“) and contained on a single line. Strings used as operands in expressions and assignments shall be treated as unsigned integer constants represented by a sequence of 8-bit ASCII values, with one 8-bit ASCII value representing one character.

1.5.1. String Representation in Verilog

In Verilog, a string is essentially a sequence of characters stored in a reg array. Each character is represented by its 8-bit ASCII value. For example:

Here:

8 represents the number of bits per character (ASCII).
14 is the maximum number of characters in the string.
The total width of the reg is 8 * 14 = 112 bits.

1.5.2. Assigning Strings

You can assign a string to a reg array using double quotes ("):

If the string is shorter than the declared length, the remaining bits are padded with zeros.

If the string is longer than the declared length, it will be truncated.

Verilog

reg [8*14-1:0] my_string; // A string of up to 14 characters

Verilog

reg [8*14-1:0] my_string;

initial begin

my_string = "Hello, World!"; // Assign a string

end

1.6 Identifier Declaration

Identifier shall be used to give an object a unique name so it can be referenced. An identifier shall either be a simple identifier or an escaped identifier.

1.6.1 Simple Identifier

It shall be any sequence of letters, digits, dollar signs ($), and the underscore characters (_).

The first character of an identifier shall not be a digit or $; it can be a letter or an underscore. Identifiers shall be case sensitive.

e.g.,

shiftreg_a

busa_index

error_condition

merge_ab

_bus3

n$657

Implementations may set a limit on the maximum length of identifiers, but they shall be at least 1024 characters. If an identifier exceeds the implementation-specified length limit, an error shall be reported.

1.6.2 Escaped Identifiers

Escaped identifiers shall start with the backslash character (\) and end with white space (space, tab, newline, or form feed).

They provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126 or 21 through 7E in hexadecimal).

Neither the leading backslash character nor the terminating white space is considered to be part of the identifier. Therefore, an escaped identifier \cpu3 is treated the same as a non-escaped identifier cpu3.

e.g.,

\busa+index

\-clock

\***error-condition***

\net1/\net2

\{a,b}

\a*(b+c)