SR (Set-Reset) Flip-Flop in Verilog – Design & Simulation
In this post, we’ll explore the SR (Set-Reset) flip-flop, understand its functionality, and implement it in Verilog HDL along with a testbench for simulation.
1. What is an SR Flip-Flop?
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An SR (Set-Reset) flip-flop is a basic edge-triggered storage element with two control inputs:
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S (Set) – forces the output Q to 1.
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R (Reset) – forces the output Q to 0.
On the active clock edge (rising edge in our case), the flip-flop updates its output according to the values of S and R.
2. Problem Statement
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Goal:
Design an edge-triggered SR flip-flop in Verilog that samples inputs S and R on the rising edge of the clock.
3. Truth Table​
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S R Q(next) Description
0 0 Q(prev) Hold
0 1 0 Reset
1 0 1 Set
1 1 X Invalid
3. Verilog Code​
Verilog
module sr_ff (
input wire S,
input wire R,
input wire clk,
output reg Q
);
always @(posedge clk) begin
case ({S,R})
2'b00: Q <= Q; // Hold
2'b01: Q <= 1'b0; // Reset
2'b10: Q <= 1'b1; // Set
2'b11: Q <= 1'bx; // Invalid
endcase
end
endmodule
Explanation:
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posedge clk ensures the flip-flop updates only on the rising clock edge.
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{S, R} is a concatenation of inputs, making the case statement cleaner.
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Invalid condition (S=1, R=1) is marked as unknown (1'bx) for simulation.
Verilog
module tb_sr_ff;
reg S, R, clk;
wire Q;
sr_ff tb_sr_ff_VM(.S(S), .R(R), .clk(clk), .Q(Q));
initial clk = 0;
always #5 clk = ~clk;
initial begin
S = 0; R = 0;
#12; S = 1; R = 0;
#10; S = 0; R = 1;
#10; S = 1; R = 1; //invalid
#10; S = 0; R = 0;
#10; $finish;
end
// Waveform dump block
initial begin
$dumpfile("tb_sr_ff.vcd");
$dumpvars(0, tb_sr_ff);
end
// Display outputs whenever any input or output changes
initial begin
$monitor("Time=%0t | S=%b R=%b clk=%b Q=%b", $time, S, R, clk, Q);
end
endmodule
Key points in testbench:
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Clock signal generated using always #5 toggles.
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Stimulus applied to verify all cases in the truth table.
6. Simulation Waveform (Expected)
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Set (S=1, R=0): Q becomes 1 at the next rising edge.
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Reset (S=0, R=1): Q becomes 0 at the next rising edge.
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Hold (S=0, R=0): Q retains its value.
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Invalid (S=1, R=1): Q goes to X (unknown).
7. Conclusion
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The SR flip-flop is a fundamental sequential logic element, and implementing it in Verilog helps in understanding both edge-triggered behavior and procedural coding style.
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Design Tip: Avoid using the S=1, R=1 state in real circuits to prevent unpredictable behavior.
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Verification Tip: Always write a testbench to confirm functionality before synthesis.
8. CLICK ON BELOW LOGO to run the Verilog Code on EDA PLAYGROUND.
