VHDL ARTICLE - [English]
- VLSI Mentor Team
- Aug 28
- 4 min read
Updated: Sep 29
Motivation
A new and exciting field is Semiconductor Engineering—making computer chips at scale.
Historically, India has done a lot of chip design, while wafer fabrication (making chips on silicon) happened in overseas foundries because building a fab needs several billions of dollars (older nodes: a few billions; advanced nodes: well over $10–20B). Now, India is also setting up fabrication and assembly/test facilities, so opportunities are expanding end-to-end.
What are the stages?
Chip Design (Front-End & Back-End design)
Front-End design: Architecture, RTL coding in HDLs (Verilog, VHDL, SystemVerilog), functional verification.
Back-End (Physical) design: Synthesis, place & route, timing/DFT, sign-off.
Chip Manufacturing
Wafer Fabrication (FEOL & BEOL) inside the fab.
Assembly, Packaging & Test (OSAT) after wafers are made.
By now, you must have already studied and understood Verilog. Let us now move to VHDL, which stands for Very High Speed Integrated Circuits Hardware Description Language.
An HDL (Hardware Description Language) is used to describe the behavior and functionality of hardware in such a way that it can be synthesized into gate-level circuits, provided there are no violations or syntax errors.
Violations can be of different types:
Timing violations (setup and hold issues)
Delays between components affecting proper outputs
Critical warnings, which if ignored, may still allow synthesis but can result in incorrect or failed outputs.
Introduction
The design of any digital system starts with writing its specifications. These originate from customer requirements and are communicated to ASIC companies through the marketing team.
Once specifications are ready, the system is designed at the block level, and later implemented at the RTL (Register Transfer Level) using coding. RTL coding can be done in VHDL, Verilog, or SystemVerilog.
Earlier, when synthesis and simulation tools were not available, designers had to verify everything manually on paper. But today, EDA (Electronic Design Automation) tools make this process much faster and more accurate.
Synthesis tools: Quartus (Intel), Vivado (Xilinx)
Simulation tools: Questa (Siemens), Xcelium (Cadence)
These tools have significantly reduced the time needed for synthesis and simulation.
Why VHDL when Verilog already exists?
VHDL is a disciplined and strongly typed language, originally developed for the U.S. Department of Defense, and inspired by the syntax of the ADA programming language.
Verilog, on the other hand, is designed with C-like syntax, making it simpler and faster to learn for engineers.
Even today, preferences vary:
Europe → VHDL is highly preferred
Defense and Aerospace → Rely on VHDL because of its strict and structured nature
VHDL enforces a strict coding style with its own structure (e.g., Entity, Architecture, Records, Libraries). Unless all the required libraries are included, synthesis cannot proceed. This ensures discipline, clarity, and reliability in the design process.
Core Concepts
Think about our daily life — we often see systems around us that take some input and produce the desired output.
For example, consider a TV: when we press the volume up/down button on the remote, the output we get is the increase or decrease in the sound level of the TV.
Here:
Input = the command sent via IR signal from the remote
Output = change in the speaker volume (measured in dB)
System Design = the logic inside the TV that processes the input and controls the power of the speaker to increase or decrease the sound.
So, from this simple daily-life example, you can understand the core concept: Every digital system takes an input and produces an output that matches the required specification.
Now, let’s take a classic digital design example: the Asynchronous Up/Down Counter.
Instead of memorizing the counter design from textbooks, let us understand it logically.
A Counter typically has the following signals:
clk (clock)
rst (reset)
counter_in (input data to load)
load (control signal to load counter_in)
enable (to allow counting)
counter_out (the output value of the counter)
Black Box:
A black box is a module where we only know the inputs and outputs.
We do not know anything about its internal components or RTL.
Based on the given specifications, we have to design the RTL for it.
RTL Diagram:
VHDL Code:
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
ENTITY counter IS
PORT (
clock : IN std_logic;
rst : IN std_logic;
ENABLE : IN std_logic;
LOAD : IN std_logic;
UP_DOWN : IN std_logic;
counter_in : IN std_logic_vector(3 DOWNTO 0);
counter_out : OUT std_logic_vector(3 DOWNTO 0)
);
END counter;
ARCHITECTURE behavioral OF counter IS
SIGNAL counter_out_tmp : unsigned(3 DOWNTO 0); -- unsigned type for arithmetic
BEGIN
counter_proc : PROCESS (rst, clock)
BEGIN
IF (rst = '0') THEN
counter_out_tmp <= (OTHERS => '0');
ELSIF rising_edge(clock) THEN
IF (LOAD = '1') THEN
counter_out_tmp <= unsigned(counter_in);
ELSIF (ENABLE = '1') THEN
IF (UP_DOWN = '1') THEN
counter_out_tmp <= counter_out_tmp + 1;
ELSE
counter_out_tmp <= counter_out_tmp - 1;
END IF;
END IF;
END IF;
END PROCESS;
counter_out <= std_logic_vector(counter_out_tmp); -- convert back
END behavioral;VIVADO ELABORATED DIAGRAM
In the advanced lectures, we will explore in detail how the RTL was designed and how it was synthesized.
Synthesis
Simulation
Applications
Communication systems (e.g., modems, encoders)
Automotive safety systems (e.g., airbag controllers)
CPU & DSP design
Space and defense hardware.
Future of VHDL
VHDL-2008: Enhanced syntax, fixed & floating-point support, and better modeling features.
Continues to be relevant alongside Verilog and SystemVerilog due to its robustness.
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