Simulation Timings
When we run a VHDL simulation, it doesn’t work like a normal program that just runs line by line. Instead, it follows an event-driven system — meaning it reacts to signal changes, timing events, and process triggers. The three main things that make it work are delta cycles, event scheduling, and signal updates.
​
When the simulation starts, the simulator first gives every signal its starting value. If a signal doesn’t have any value, it gets 'U' (undefined). If you wrote something like := '0', then it starts with '0'. After this, all processes in your design start running for the first time. Each process runs until it hits a wait statement. For example, if you have signal clk : std_logic := '0'; signal rst : std_logic := '0';, then at the beginning of simulation, both will have value '0'.
​
Now comes the first step called the delta cycle. At this point, the simulator checks which processes need to run. For example, if you have
clk <= not clk after 5 ns;
the simulator understands that the clock should change to '1' after 5 nanoseconds. It saves that event for later — for time = 5 ns. But right now, time is still 0 ns. This is called delta 0 — no real time passes here, the simulator just plans what will happen later.
​
The simulator keeps all these events in something called an event queue (you can imagine it like a to-do list). For example,
-
0 ns — initialize signals
-
5 ns — toggle clk
-
10 ns — toggle clk again
Whenever you use after or wait for, the simulator adds that event into this list for future execution.
​
When the time for an event comes, like at 5 ns, the simulator moves to the signal update phase. This means it looks at the list and updates all signals that are supposed to change. For example, if the event says clk should change to '1', then at that exact moment, the simulator updates it. Once clk changes, any process that depends on clk — like a flip-flop — runs again.
​
After the signal updates, the simulator goes into the process execution phase. Here, it runs all the processes that are sensitive to the changed signals. For example,
​
process(clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
When clk becomes '1', a rising edge happens and the process runs again. It executes q <= d;, but note — q doesn’t change right away. The simulator waits for the next delta cycle to update q. This delay helps make sure all signals settle correctly before time moves forward.
​
Now the simulator checks if there are still any signals that need to change at this same time. If yes, it keeps running more delta cycles (Δ1, Δ2, and so on). When everything is stable, it finally moves forward in time.
​
For example, if the current time is 0 ns and the next event is scheduled at 5 ns, the simulator jumps straight to 5 ns. Then it repeats the same cycle again — signal updates, process execution, delta stabilization, and so on.
​
At the end, when there are no more events left in the list, the simulator stops. That means there are no more signals to change and no processes waiting to run. It displays a message like “No more events to simulate”, and the simulation ends.
In simple words, the simulator works in small invisible steps. It updates signals, runs processes, waits for them to settle, and then moves time forward. It keeps repeating this until there’s nothing left to do. This is how VHDL handles timing so precisely — every tiny signal change is tracked and simulated step by step.